The present invention relates generally to integrated circuit design, and more particularly, relates to a system and method to measure local variation and well proximity effects on integrated circuits.
Traditionally, variations in the operational characteristics of field effect transistors (FETs) occurs even though the FETs array have common designs and are fabricated with common processing conditions, which is generally referred to as mismatch. Mismatch results from either systematic or stochastic (random) effects. In several instances, random mismatch dominates the effects of systemic mismatch and primarily results from local variations in dopant concentrations, mobility, oxide thickness and polysilicon granularity. As a result of mismatch, the operational characteristics of FETs that may vary include gate threshold voltage, Vt, current saturation, Idsat, and transconductance, Gm.
Another well known contributor to dopant concentration mismatch is caused by the well proximity effect (WPE). The WPE causes the gate threshold voltage, Vt, of the FETs to change as a function of the distance from an edge of the well. This occurs during an implant process in which dopant atoms are implanted into a substrate with high energy to form deep retrograde well profiles in furtherance of providing latch-up protection and suppress lateral punch-though that occurs in (FETs). The WPE has been show to affect the threshold voltage of FETs more than one micrometer from the well edge.
Failure to entertain random mismatch or WPE when designing FETs has resulted in FETs being susceptible to electrical noise that may lead to failure of the electronic circuit in which the FETs are formed. Additionally, catastrophic failure has resulted from WPE when designing current mirrors due to the same shifting out of saturation mode as a result of WPE.
As a result, it is desired to examine local variations and WPE by measuring threshold voltage, saturation current and transconductance. The standard deviations of these measurements are used to determine a linear distribution that follows the square root of the transistor width and length for measuring local variation. This is achieved by examining pair of FETs, which due to silicon area limitation, the number of pairs being limited. As a result, statistical significance is achieved by pooling data from multiple pairs of transistors, i.e., dices, and wafers. The data carries information of local variation and die-die variation, i.e. confounding effect. The standard deviations may have considerable variation from wafer to wafer and lot to lot. To ameliorate wafer-to-wafer and lot-to-lot variations proposed have been test structures employing FET arrays have been implemented to characterize local variation. However, periphery circuits are typically needed to access individual transistors to undertake the measurements. At early stages of process development, such a circuit is not readily available.
As a result, a need exists, for providing local variation and WPE measurement techniques.